The present disclosure relates in general to the field of processing systems, and in particular to processing systems for cryptographic applications.
In the U.S. Pat. No. 7,506,017 B1, entitled “VERIFIABLE MULTIMODE MULTIPLIERS” and issued to Dupenloup, a verifiable duplex multiplier circuit is disclosed. In one mode, the circuitry of the duplex multiplier functions as an N-bit×N-bit multiplier. In another mode, the circuitry of the duplex multiplier operates as dual (N/2)-bit×(N/2)-bit multipliers. Because the same circuitry can be used to serve as both an N×N multiplier and as dual N/2×N/2 multipliers, integrated circuit resources are conserved. The duplex multiplier circuitry uses an architecture that can be automatically synthesized using a logic synthesis tool. Verification operations can be performed using logic-equivalency error checking tools. Exhaustive verification is possible using this approach, even when relatively large duplex multipliers (e.g., duplex multipliers with N values of 16 or more) are used.
In U.S. Pat. No. 7,024,444 B1, entitled “SPLIT MULTIPLIER ARRAY AND METHOD OF OPERATION” and issued to Green, a multiplier circuit for use in a data processor is disclosed. The multiplier circuit comprises a partial products generating circuit that receives a multiplicand value and a multiplier value and generates a group of partial products. The multiplier circuit also comprises a split array for adding the partial products. A first summation array comprises a first group of adders that sum the even partial products to produce an even summation value. A second summation array comprises a second group of adders that sum the odd partial products to produce an odd summation value. The even and odd summation values are then summed to produce the output of the multiplier.